Introduction

Registers are value containers which reside on the CPU (separately from RAM). They are small in size and some have special purposes. x86-64 assembly operates with 16 general-purpose registers (GPRs). It should be noted that the 8-byte (r) variants do not exist in 32-bit mode.

64-bit RegisterLower 4 BytesLower 2 BytesLower 1 Byte
rbpebpbpbpl
rspespspspl
ripeip
raxeaxaxal
rbxebxbxbl
rcxecxcxcl
rdxedxdxdl
rsiesisisil
rdiedididil
r8r8dr8wr8b
r9r9dr9wr9b
r10r10dr10wr10b
r11r11dr11wr11b
r12r12dr12wr12b
r13r13dr13wr13b
r14r14dr14wr14b
r15r15dr15wr15b

Each row contains names which refer to different parts of the same register. Note, the lower 16 bits of the rip register (instruction pointer) are inaccessible on their own.

For example, the rax register could be set to the following:

rax = 0x0000 000AB 10CA 07F0

The name eax would then only refer to the part of the rax register which contains 10CA 07F0. Similarly, ax would represent 07F0, and al would be just F0.

Additionally, the upper byte of ax, bx, cx and dx may be separately accessed by means of the ah, bh, ch and dh monikers, which exist for legacy reasons.

Register Specialisation

Not all registers available in the x86-64 paradigm are created equal. Certain registers are reserved for specific purposes, despite being called general-purpose.

The Stack Pointer rsp

The stack pointer rsp (esp for 32-bit machines) is used to point to the current top of the stack and should not be used for any other purpose other than in instructions which involve stack manipulation.

The Base Pointer rbp

The base pointer rbp (ebp for 32-bit machines) is the twin brother of the stack pointer and is used as a base pointer when calling functions. It points to the beginning of the current function's stack frame. Interestingly enough, its use is actually gratuitous because compilers can manage the stack frames of functions equally well without a separate base pointer. It is mostly used to make assembly code more comprehensible for humans.

The Instruction Pointer rip

The instruction pointer rip (eip for 32-bit machines) points to the next instruction to be executed. It is paramount not to get confused when using a debugger, since the rip does not actually point to the instruction currently being executed.

The Flag Register rFlags

The flag register rFlags (eFlags for 32-bit machines) is an isolated register which is automatically updated by the CPU after every instruction and is not directly accessible by programmes. Following is a table of the meaning assigned to different bits of this register. Note that only the lower 32 bits are used even on 64-bit machines.

NameSymbolBitUsage=1=0
CarryCF0Indicates whether the previous operation resulted in a carry-over.CY (Carry)CN (No Carry)
1Reserved. Always set to 1 for eFlags.
ParityPF2Indicates whether the least significant byte of the previous instruction's result has an even number of 1's.PE (Parity Even)PO (Parity Odd)
3Reserved.
Auxiliary CarryAF4Used to support binary-coded decimal operations.AC (Auxiliary Carry)NA (No Auxiliary Carry)
5Reserved.
ZeroZF6Indicates whether the previous operation resulted in a zero.ZR (Zero)NZ (Not Zero)
SignSF7Indicates whether the most significant bit was set to 1 in the previous operation (implies a negative result in signed-data contexts).NG (Negative)PL (Positive)
TrapTF8Used by debuggers when single-stepping through a programme.
Interrupt EnableIF9Indicates whether or not the CPU should immediately respond to maskable hardware interrupts.EI (Enable Interrupt)DI (Disable Interrupt)
DirectionDF10Indicates the direction in which several bytes of data should be copied from one location to another.DN (Down)UP (Up)
OverflowOF11Indicates whether the previous operation resulted in an integer overflow.OV (Overflow)NV (No Overflow)
I/O Privilege LevelIOPL12-13
Nested TaskNT14
ModeMD15
ResumeRF16
Virtual 8086 ModeVM17
31-63Reserved.

Floating-Point Registers and SSE

In addition to the aforementioned registers, the x86-64 paradigm includes 16 registers, xmm[0-15], which are used for 32- and 64-bit floating-point operations. Furthermore, the same registers are used to support the Streaming SIMD Extensions (SSE) which allow for the execution of Single Instruction Multiple Data (SIMD) instructions.